The present invention relates to semiconductor integrated circuits, and more particularly concerns a physical configuration for the elements of a very large scale integration (VLSI) chip.
Presently available digital VLSI chips use a "master image" or "master slice approach" in which individual logic circuits are laid out in predefined cells and then wired together with a multi-layer pattern of conductors to achieve the final overall design. The chips themselves are rectangular, usually nearly square in shape.
Prior-art chips configure the individual logic cells in a series of straight columns across the chip. The columns are separated by straight wiring bays containing the inter-cell conductors. A group of input/output (I/O) cells contain higher-powered drivers and signal-conversion receivers for coupling to off-chip circuits. These cells are placed around the periphery of the chip, where they can be made larger and can connect to pins or other external contacts leading away from the chip.
This configuration has several problems. The centers of the wiring bays tend to fill up with conductors while the ends are still relatively unused, wasting space at the ends--or, alternatively, requiring wider bays and thus fewer logic cells on the chip. Also, prior chips usually use only two levels of wiring, although present technology would permit three. With the usual almost-square overall chip shape, columnar layouts need about the same number of conductors along the wiring bays as across them; a third level would provide space for many more wires in one direction than in the other, so much of it would remain empty. A further problem concerns thermal cycling. As the chip heats an cools, it expands and contracts, usually at a different rate than the substrate to which it is mechanically (as well as electrically) coupled. Placing the contacts at the outside of the chip maximizes the stresses between chip and substrate during cycling, because their distances from a "neutral point" (DNP) on the chip is great. Even when the actual off-chip contacts are moved inward to reduce the DNP, wiring space is wasted bussing signals to the interior of the chip and distributing power outward in an inefficient manner. Moreover, prior chip layouts are inflexible, in that a change in chip size with enhanced technology or greater functionality requires a major redesign of almost every physical parameter of the chip: different power bussing, different spacings, and a complete rework of the I/O cells at the periphery. And, of course, changing the I/O cells changes the chip footprint, necessitating a redesign of the substrate wiring. If a third metal layer were used to alleviate this problem, it would have to be dedicated almost entirely for I/O wiring, leaving very little for signal wiring.
A few chip layouts have used other than straight columns of cells and other than wholly peripheral I/O cells. These approaches, however, have not addressed the above problems, and have not alleviated them in any significant way. U.S. patent application Ser. No. 533,383 and now U.S. Pat. No. 4,575,744 L. B. Caldwell, al, describes L-shaped columns of logic cells each having a single bend, and a chip having such columns in quadrants, giving an overall cross shape. The purpose of this configuration is to provide greater wiring flexibility. Power is bussed conventionally, and the I/O cells remain at the periphery. U.S. Pat. No. 3,751,720 to Nestork shows a circular chip layout. The cells lie in wedge-shaped segments, and the I/O cells are peripheral. Circuit density is necessarily low, and additional similar cells cannot be accommodated at all. U.S. Pat. No. 3,714,527 to Schmidt arranges random circuits in a circle around a central on-chip heater. The purpose of this is merely to achieve a known, constant chip temperature for electrical accuracy. Japanese kokai No. 53-78185 of Fujitsu K.K. shows a single rectangular array of driver circuits separated from a chip periphery by a single wiring bay, and a method of connecting the drivers to each other.